1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit and, more particularly, to reduction in lock-up time.
2. Description of the Background Art
FIG. 12 is a circuit diagram of a conventional PLL circuit. The PLL circuit comprises a phase comparator 30, a charge pump circuit 31, an LPF 1, a VCO (voltage-controlled oscillator) 2, and a frequency divider 4, as shown in FIG. 12.
The phase comparator 30 includes nine NAND gates T1 to T9. The NAND gates T1 and T2 are three-input NAND gates, and the NAND gate T3 is a four-input NAND gate, the NAND gates T4 to T9 being two-input NAND gates.
Referring to FIG. 12, reference character I1 designates an input signal, and I2 designates a reference signal. The input signal I1 is accepted by a first input of the NAND gate T4. The output of the NAND gate T4 is applied to a first input of the NAND gate T1, a first input of the NAND gate T3, and a first input of the NAND gate T5. The output of the NAND gate T5 is applied to a second input of the NAND gate T1, a second input of the NAND gate T3, and a first input of the NAND gate T6. The output of the NAND gate T6 is fed back to a second input of the NAND gate T5.
The reference signal I2 is accepted by a first input of the NAND gate T9. The output of the NAND gate T9 is applied to a first input of the NAND gate T2, a third input of the NAND gate T3, and a first input of the NAND gate T8. The output of the NAND gate T8 is applied to a second input of the NAND gate T2, a fourth input of the NAND gate T3, and a first input of the NAND gate T7. The output of the NAND gate T7 is fed back to a second input of the NAND gate T8.
An output signal S3 from the NAND gate T3 is applied to the input of a delay circuit 3 which, in turn, adds a predetermined time delay to the signal S3 and then outputs a delay signal S3' to a third input of the NAND gate T1, a third input of the NAND gate T2, a second input of the NAND gate T6, and a second input of the NAND gate T7 through a node N1.
There are provided signals Q1 and Q2 outputted respectively from the NAND gates T1 and T2 in the form of phase comparison output signals.
The NAND gates T1 to T9 are connected in the foregoing manner. The NAND gates T1 and T4 form a first flip-flop, and the NAND gates T5 and T6 form a second flip-flop. The NAND gates T2 and T9 form a third flip-flop, and the NAND gates T7 ad T8 form a fourth flip-flop.
When the phase of the input signal I1 lags that of the reference signal I2, the phase comparator 30 as above constructed outputs the phase comparison output signal Q2 at L level of a pulse width proportional to the phase lag. Conversely, when the phase of the input signal I1 leads that of the reference signal I2, the phase comparator 30 outputs the phase comparison output signal Q1 at L level of a pulse width proportional to the phase lead.
FIG. 13 is a waveform chart showing the phase comparison of the phase comparator 30 of FIG. 12. When the phase of the input signal I1 leads that of the reference signal 12 by a time TG as shown in FIG. 13, an L-level pulse of the phase comparison output signal Q1 has a width (TG+.DELTA.T) and an L-level pulse of the phase comparison output signal Q2 has a width .DELTA.T.
The pulse width .DELTA.T is a delay time by the delay circuit 3. The L-level pulses of the phase comparison output signals Q1 and Q2 of the phase comparator 30 are adapted to additionally contain the pulse width .DELTA.T in this manner for the purpose of placing into responsive normal operation the charge pump circuit 31 receiving the phase comparison output signals Q1 and Q2. The pulse width .DELTA.T, if small, increases the likelihood that the charge pump circuit 31 enters the dead zone.
The charge pump circuit 31 which follows the phase comparator 30 includes a PMOS transistor T11, an NMOS transistor T12, a variable current source .PHI.IA, and a variable current source .PHI.IB. The PMOS transistor T11 and NMOS transistor T12 are connected in series. The variable current source .PHI.IA is connected between the source of the PMOS transistor T11 and a power supply V.sub.cc, and the variable current source .PHI.IB is connected between the source of the NMOS transistor T12 and the ground. A signal given from a node N31 between the drain of the PMOS transistor T11 and the drain of the NMOS transistor T12 is a comparison voltage signal S31 of the charge pump circuit 31.
The phase comparison output signal Q1 from the phase comparator 30 is applied to the gate of the PMOS transistor T11. The phase comparison output signal Q2 is applied to an inverter T10 which in turn outputs the inverted phase comparison output signal Q2 to the gate of the NMOS transistor T12.
The variable current source .PHI.IA varies a supply current IA of the PMOS transistor T11 in response to a control signal C1, and the variable current source .PHI.IB controls a supply current (sink current) IB of the NMOS transistor T12 in response to the control signal C1. The control signal C1 is an external signal given from a microcomputer, a lock detector or the like and indicates a relatively large current supply when lock starts, while indicating a relatively small current supply after lock is completed.
One of the PMOS and NMOS transistors T11 and T12 is on for a time period corresponding to the phase difference between the input signal I1 and the reference signal I2 in response to the phase comparison output signal Q1 and the inverted phase comparison output signal Q2 whereby the charge pump circuit 31 outputs the comparison voltage signal S31 whose voltage value indicates the logical level "H" or "L".
The LPF 1 filters the comparison voltage signal S31 from the charge pump circuit 31 to apply a control voltage V1 to the VCO 2 which in turn oscillates at an oscillation frequency based on the control voltage V1 to output an output signal S2 to the frequency divider 4.
The frequency divider 4 applies the signal given by frequency-dividing the output signal S2 from the VCO 2 to the first input of the NAND gate T4 in the form of the input signal I1. In this way, the PLL circuit is formed which comprises the phase comparator 30, the charge pump circuit 31, the LPF 1, the VCO 2 and the frequency divider 4.
As a microcomputer or the like detects the lock start time from turn-on time of the power supply, the PLL circuit applies the control signal C1 indicative of large current supply to the variable current sources .PHI.IA and .PHI.IB of the charge pump circuit 31. As a result, the charge pump circuit 31 performs a large current supply operation for providing relatively large amounts of the supply currents IA and IB, thereby to increase the loop gain of the PLL circuit. Then the PLL circuit becomes locked at high speeds.
Then the microcomputer applies the control signal C1 indicative of small current supply to the variable current sources .PHI.IA and .PHI.IB of the charge pump circuit 31 after a given time has elapsed since the lock start time. When lock is completed, the charge pump circuit 31 performs a small current supply operation for providing relatively small amounts of the supply currents IA and IB, whereby the PLL circuit has a good C/N (carrier-to-noise ratio).
The provision of the delay circuit 3 in the phase comparator 30 prevents the pulse width of the phase comparison output signals Q1 and Q2Q2) from entering the dead zone which is a time period for which the charge pump circuit 31 cannot normally generate the comparison voltage signal S31, if the phase of the input signal I1 approaches that of the reference signal I2.
The length (of the duration) of the dead zone of the charge pump circuit 31 is negatively correlated with the supply current amounts IA and IB of the variable current sources .PHI.IA and .PHI.IB. The dead zone is short when the supply current amount is large, and the dead zone is long when the supply current amount is small. The delay circuit 3 has a given delay time.
When the charge pump circuit 31 has a small amount of supply current, too short delay time results in the dead zone problem. Conversely, when the charge pump circuit 31 has a large amount of supply current, too long delay time results in poor C/N of the PLL circuit.
This causes restriction of circuit design such as restriction of the supply current amount of the charge pump circuit 31. The PLL circuit has not been achieved which has a reduced lock-up time and a good C/N.